Kerfless epitaxial silicon wafers with 7ms carrier lifetimes and a wide lift-off process window
- authored by
- Catherin Gemmel, Jan Hensen, Lasse David, Sarah Kajari-Schröder, Rolf Brendel
- Abstract
Silicon wafers contribute significantly to the photovoltaic module cost. Kerfless silicon wafers that grow epitaxially on porous silicon (PSI) and are subsequently detached from the growth substrate are a promising lower cost drop-in replacement for standard Czochralski (Cz) wafers. However, a wide technological processing window appears to be a challenge for this process. This holds in particularly for the etching current density of the separation layer that leads to lift-off failures if it is too large or too low. Here we present kerfless PSI wafers of high electronic quality that we fabricate on weakly reorganized porous Si with etch current densities varying in a wide process window from 110 to 150 mA/cm2. We are able to detach all 17 out of 17 epitaxial wafers. All wafers exhibit charge carrier lifetimes in the range of 1.9 to 4.3 ms at an injection level of 1015 cm%3 without additional high-temperature treatment. We find even higher lifetimes in the range of 4.6 to 7.0 ms after applying phosphorous gettering. These results indicate that a weak reorganization of the porous layer can be beneficial for a large lift-off process window while still allowing for high carrier lifetimes.
- Organisation(s)
-
Solar Energy Section
- External Organisation(s)
-
Institute for Solar Energy Research (ISFH)
- Type
- Article
- Journal
- Japanese Journal of Applied Physics
- Volume
- 57
- ISSN
- 0021-4922
- Publication date
- 04.2018
- Publication status
- Published
- Peer reviewed
- Yes
- ASJC Scopus subject areas
- General Engineering, General Physics and Astronomy
- Sustainable Development Goals
- SDG 7 - Affordable and Clean Energy
- Electronic version(s)
-
https://doi.org/10.7567/JJAP.57.041301 (Access:
Closed)
