Algorithmen und Hardware-Architekturen zur LED-Flickerunterdrückung in videobasierten Fahrerassistenzsystemen

Compared to mechanical mirrors on vehicles and trucks, new camera monitor systems offer several advantages. The observation of the vehicle’s surroundings with application-optimized optics can minimize the blind spot and the video data captured by a digital camera sensor can be used in other driver assistance systems. The smaller design of the camera module outside the vehicle can also reduce wind resistance and consequently the vehicle’s fuel consumption while driving. However, the discrete scanning of the image sensor leads to alias effects when recording modulated light sources, which can disturb and distract the driver in the form of flickering when displayed on the monitor (instead of the mechanical mirror). The artifact-free reproduction of the environment is therefore necessary for the approval of new camera monitor systems, which requires the suppression of flicker artifacts without generating other image artifacts. In addition, the stepwise processing of video data with low latency and sufficient throughput at low energy consumption is required. This paper presents a technical solution for the suppression of flicker artifacts for use in camera monitor systems. In the first step, the human perception of flicker artifacts in the context of the novel application was investigated by means of psychophysical studies. The quantitative measurements were then used to derive algorithmic requirements for flicker suppression and suitable metrics for assessing the quality of flicker suppression. A novel algorithm developed in this work first masks pixels affected by flicker (flicker detection) before they are selectively filtered (flicker suppression). The process is based on a temporally motion-compensated filtering of several consecutive individual images. A predictive block matching algorithm is used for motion compensation, which has been optimized with regard to flicker resistance. The implementation of the developed algorithms in a vehicle with requirements for real-time processing and low energy consumption requires specialized hardware architectures. The results of this work show that an implementation on a digital signal processor and a field programmable gate array (FPGA) can fulfill these requirements.